D. Priya ¹, J. Arunarasi ¹, A. Arul Mary ¹

Affiliations
1 Department of ECE, Vel Tech Multitech, Avadi, Chennai – 54, Tamil Nadu, IN

Abstract

Objective: Technology trend are one of the most important to use the bulky on-chip memories such as level-2 (L2) and level-3 (L3) cache. In this paper, Non-Uniform Cache access Architectures (NUCA) has been used in order to decrease the effects of the high access latencies. For the systems which operate at high frequency, the latencies of such caches are conquered by wire delays. Methods: In this architecture,   several banks are partitioned and which is connected to the controller through switches and links. This larger cache memory increases overall wire delays across the chip due to very bulky latencies. The majority of the access time will not absorb them self and that occupy in the routing to and from the several banks. The predictable lower-level caches have the best ever access time among the entire the sub arrays, although such uniform cache access don’t make the use of differences in latencies of the entire sub arrays. Findings: Hence there is a necessitate for non-uniform cache architectures where the cache memories  is broken down into several banks that can be analyzed at dissimilar latencies and resulting in diminish of energy and power consumption. Applications/Improvements: An experimental result shows the comparison of NUCA and UCA using SRAM/MRAM in terms of power and energy.

Keywords

Chip Multiprocessors, Non Uniform Cache Access, Uniform Access

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A. Karthikeyan ¹, J. Arunarasi ¹, A. Arul Mary ¹

Affiliations
1 Department of Electronics and Communication Engineering, Vel Tech Multitech, Avadi, Chennai – 600062, Tamil Nadu, IN

Abstract

Objective: This paper discusses different ways of power consumption in FPGA and the earlier SRAM based power reduction techniques with its limitations and demonstrates the methodology adapted by the proposed neoteric Memristor based FPGA architecture. The programmable interconnects of Memristor based FPGA architecture uses the newly found circuit element, i.e. Memristor instead of the SRAM based interconnects as in the usual FPGA architecture, resulting in significant reduction of overall power consumption, area, propagation delay which in turn increases the speed of FPGA than the other conventional SRAM based FPGA architecture. Statistical Methods: The study on the various architectures of FPGA aiming at minimizing the power consumption with the application of different techniques is carried out earlier. One such technique is the SRAM power reduction technique which has got its own limitations such as low density, longer routing path, increased propagation delay, increased peak power consumption rate as well as high value of average power consumption. This paper proposes a low area with the help of Memristor in order to such a minimal routing path aiming to reduce the drawbacks as identified in SRAM architecture. Findings: A simulation work has been carried out with the help of HSPICE and the results prove that the peak power consumption, average power consumption, propagation delay are reduced to a larger extent than that of the reported SRAM architecture. Applications/Improvements: Further it is recorded that the Memristor based FPGA architecture suits better for the applications where there is minimal energy requirement on wireless network scenarios.

Keywords

CMOS Technologies, Field-Programmable Gate Arrays (FPGA), Low Power Consumption, Memristor, SRAM, Very Large Scale Integrated Circuits

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